Sd/Mmc Host Controller - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

17. SD/MMC HOST CONTROLLER

S5PV210 has three slots for supporting high speed SD/MMC interface. SDMMC0 as 4-bit/8-bit MMC interface,
SDMMC1 support 4-bit MMC interfaces. Every MMC controller belongs to VDD_EXT0/1/2 power.
17.1. Signal Description
Signal
SD0/1/2/3_CLK
SD0/1/2/3_CMD
SD0/1/2/3_CDn
SD0/1/2/3_DATA[3:0]
17.2. Muxed Signal usage
Channel 0
Channel 1
Channel 2*
Channel 3*
Every controller has up to 52MHz speed. So clock and data line should have same routing path.
(1) Voltage level should be the same between device and SD/MMC IO(VDD_EXT0/1/2 ).
Ch 0,1 belongs VDD_EXT0 power domain. Ch2 belongs VDD_EXT1. Ch3 belongs VDD_EXT2
(2) Add a 10K-external pull-up resistor to CMD line needs. And add 51K-external pull-up resistors to Data line.
(3) MMC channel 0 shares data lines with MMC channel 1 and MMC channel 2 shares data lines with MMC
channel 3. So it is impossible that CH0(or CH2) 8bit and CH1(or CH3) are used at the same time.
(4) DAT[3] card detection method didn't recommend by following issues.
i) Difficult to detect when card is removed during operation.
ii) Pull-down resistor of dat3 cause different impedance between data lines.
iii) Some cards don't have enough internal pull-up resistors.
(5) SDMMC CH2 can be used for iROM second booting. So SD card slot is better to connect to CH2 for debugging.
I/O
O CLOCK (SD/SDIO/MMC card interface channel 0)
IO COMMAND/RESPONSE (SD/SDIO/MMC card interface channel 0)
I CARD DETECT (SD/SDIO/MMC card interface channel 0)
IO DATA[3:0] (SD/SDIO/MMC card interface channel 0)
Case 1 (4 Channel Usage)
4-bit mode
4-bit mode
4-bit mode
4-bit mode
Description
Case 2 (2 Channel Usage)
8-bit mode
Not available
8-bit mode
Not available
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