Feature Of The Irom Boot Mode - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

4.3. Feature of the IROM Boot mode

- Overview
C110 iROM boot has two step boot mode. First is a normal memory boot and second is SDMMC CH2 boot.
(OneNand, Nand, SDMMC_CH0 these kinds of memories are used for first boot.)
If first boot is failed, boot sequence moves to SDMMC CH2. The first boot fail cases are checksum Error and SDMMC
init error etc, Refer to iROM application note.
1. OneNAND :
- Xm0CSn4/NFCSn2/ONANDXL_CSn0 signal should be used for boot
2. NAND :
- Using S/W 8bit ECC at boot page
- S5PV210 supports 16bit ECC in case of 4KB, 5cycle Nand type,.
- Xm0CSn2/NFCSn0 signal should be used for boot
3. SD/MMC and eMMC :
- SDMMC CH0 is used for first 4bit boot.
- SDMMC CH2 is used for second boot
4. eMMC boot :
- SD/MMC CH0 is used for eMMC boot(4/8 bit). Bus width is controlled by OM setting
5. UART boot :
- UART CH2 is used for UART boot and Debug message
Note) OM[4:0] signal don't need a pull-up/down register. But OM[5] signal needs a pull-down register. This register
intends to change a boot mode between Normal storage and UART/USB boot.
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