Syscon - Samsung S5PV210 Hardware Design Manual

S5PV210_HARDWARE DESING GUIDE REV 1.0

4. SYSCON

4.1. Signal Description
- JTAG (Dedicated signal)
Ball Name
XJTRSTN
XJTMS
XJTCK
XJTDI
XJTDO
XJDBGSEL
Note) JTAG signals don't need external pull-up/down registers. Because C110 has internal pull-up/down registers for
JTAG signal.
- RESET / ETC (Dedicated signal)
Ball Name
XOM_0 ~ XOM_5
XDDR2SEL
XPWRRGTON
XNRESET
XCLKOUT
XNRSTOUT
XNWRESET
XRTCCLKO
Xepllfilter
I/O Description
XjTRSTn (TAP Controller Reset) resets the TAP controller at start.
I
XjTMS (TAP Controller Mode Select) controls the sequence of the TAP controller's
I
states.
XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic.
I
XjTDI (TAP Controller Data Input) is the serial input for test instructions and data.
I
XjTDO (TAP Controller Data Output) is the serial output for test instructions and data.
O
I JTAG selection. 0: Cortex A8 Core JTAG, 1: Peripherals JTAG
I/O Description
Operating Mode control signals (6bit)
I
I Selection DDR type (LPDDR1/2 or DDR2)
O Power Regulator enable
System Reset
I
O Clock out signal
For External device reset control
O
System Warm Reset.
I
RTC Clock out
O
1.8nF capacitance for EPLL Filter
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