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S5PV210_HARDWARE DESING GUIDE REV 1.0
5. MEMORY SUBSYSTEM
5.1. Signal Description
Signal
XDDR2SEL
Xm1SCLK, Xm2SCLK
Xm1nSCLK, Xm2nSCLK
Xm1RASn, Xm2RASn
Xm1CASn, Xm2CASn
Xm1WEn, Xm2WEn
Xm1DATA[31:0], Xm2DATA[31:0]
Xm1DQM[3:0], Xm2DQM[3:0]
Xm1DQS[3:0], Xm2DQS[3:0]
Xm1DQSn[3:0], Xm2DQSn[3:0]
ADCT[18:0](Address & Control),
CKE
5.2. TQ : Temperature Indicator
Samsung mDDR includes the enhanced feature, Temperature Indicator (TQ), which informs MDRAM's internal
temperature of controller, in order to notice that DRAM inside temperature become higher than 85'C which is the
highest temperature guaranteed normally in the specification. In over 85'C, DRAM refresh cycle is derated according
as the temperature goes up, controllers need to adjust auto-refresh cycle based on MDRAM temperature. Generally, it
is well known that the auto-refresh cycle of DRAM tends to be half every 10'C up over 85'C. The guidance for auto-
refresh cycle over 85'C is provided by specification.
Temp
Auto-Refresh cycle
-25 ~ 85C
7.8us
85 ~ 95 C
3.9us
5.3. PCB LAYOUT GUIDELINES FOR MEMORY
I/O
I
Memory Type Selection (0; LPDDR1, 1: DDR2, LPDDR2)
O
Memory Clock
O
Memory Negative Clock
O
Row Address Selection
O
Column Address Selection
O
Write Enable
I/O
Memory Data Bus
O
Write Masking Per Byte
I/O
Data Strobe Signal Per Byte
I/O
Data Strobe Negative Signal Per Byte
Memory Address, Bank Address, CS, CKE signals
O
Mobile
DRAM
Description
TQ
S5PV2
10
CMD
Block diagram for TQ
85
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