Table of Contents
Advertisement
R
Parallel Cable IV Interface
The Parallel Cable IV (PC IV) download cable can also be used to program the XC2VP30.
The pinout provided in
solution.
Figure 2-7
System ACE JTAG Configuration Interface
The JTAG Configuration port on the System ACE device is connected directly to the JTAG
interface of the XC2VP30
to the XC2VP30.
Table 2-5: JTAG Connection from System ACE to XC2VP30
FPGA_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS
GPIO LEDs and LCD
GPIO
The ML310 Hardware Platform provides direct GPIO access to eight LEDs for general
purpose use and provides indirect access to a 16 pin connector (J13) used to interface the
ML310 with a 2 Line by 16 character LCD Display, AND491GST. Access to the GPIO lines
is handled by a simple register interface that is connected XC2VP30 GPIO signals.
Figure 2-8
The user also has an indirect access path to more GPIO capability via PCI Bus accesses
when controlling the GPIO header (J5) connected to the ALi M1535D+ South Bridge.
Please refer to section
programming and controlling the ALi M1535D+ GPIO port.
30
Chapter 2: ML310 Embedded Development Platform
Figure 2-7
is compatible with the PC IV JTAG programming
shows the pinout of the PC IV JTAG connector.
GND
GND
GND
GND
PC4_TDI
SYSACE_TSTTDO
Figure 2-7: PC4 IV JTAG Connector Pinout
device.Table 2-5
Pin Name
System ACE (U38)
80
81
82
85
shows the connectivity of the ML310 LEDs and LCD.
"ALi South Bridge Interface, M1535D+, U15"
www.xilinx.com
1-800-255-7778
Get other manuals https://www.bkmanuals.com
GND
GND
GND
13
1
14
2
NC
VCCV3
NC
PC4_TMS
PC4_TCK
UG000_05_21_082802
shows the JTAG connections from System ACE
G7
F5
F26
H8
UG068 (v1.01) August 25, 2004
XC2VP30 (U37)
for more details on
ML310 User Guide
Advertisement
Table of Contents
