Chapter 2: Configuration Options; Jtag Configuration; Jtag Chain - Xilinx XtremeDSP Spartan-3A DSP 3400A HW-SD3400A-DSP-DB-UNI-G User Manual

Configuration Options

JTAG Configuration

JTAG Chain

Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
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This chapter provides an overview of the four ways the FPGA on the Spartan-3A DSP
3400A Edition board can be configured:
•
Xilinx download cable (JTAG)
•
System ACE controller (JTAG)
•
Board flash memory
•
SPI flash memory
The FPGA, the board flash memory, and the CPLD can all be configured through the JTAG
port of the Spartan-3A DSP 3400A Edition board, as illustrated in
X-Ref Target - Figure 2-1
Board Flash Memory
TDI TDO
Figure 2-1:
The JTAG chain starts at the JTAG header (see
•
the System ACE controller
•
the board flash memory
•
the FPGA
•
the CPLD
•
the FMC expansion connector
The chain bypasses the FMC expansion connector if no expansion module is present.
Jumper JP4 must not be populated for appropriate JTAG operation.
The JTAG chain can be used to program the FPGA and to access the FPGA for hardware
and software troubleshooting. The JTAG header's connection to the JTAG chain allows a
host computer to transfer bitstreams to the FPGA using iMPACT from Xilinx. The JTAG
header also allows such troubleshooting tools as ChipScope Pro to access the FPGA.
System ACE
CPLD Controller
TDI TDO TSTDI CFGTDO
TSTDO CFGTDI
Spartan-3A DSP 3400A Edition Board JTAG Chain
25. JTAG
www.xilinx.com
Chapter 2
Figure 2-1.
FPGA FMC #1
TDI TDO TDI TDO TDI
Header) and goes through
FMC #2
TDO
45