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Parallel Cable IV Interface
System ACE JTAG Configuration Interface
GPIO LEDs and LCD
GPIO
30
All manuals and user guides at all-guides.com
The Parallel Cable IV (PC IV) download cable can also be used to program the XC2VP30.
The pinout provided in
Figure 2-7
solution.
Figure 2-7
shows the pinout of the PC IV JTAG connector.
SYSACE_TSTTDO
Figure 2-7: PC4 IV JTAG Connector Pinout
The JTAG Configuration port on the System ACE device is connected directly to the JTAG
interface of the XC2VP30
to the XC2VP30.
Table 2-5: JTAG Connection from System ACE to XC2VP30
Pin Name
FPGA_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS
The ML310 Hardware Platform provides direct GPIO access to eight LEDs for general
purpose use and provides indirect access to a 16 pin connector (J13) used to interface the
ML310 with a 2 Line by 16 character LCD Display, AND491GST. Access to the GPIO lines
is handled by a simple register interface that is connected XC2VP30 GPIO signals.
Figure 2-8
shows the connectivity of the ML310 LEDs and LCD.
The user also has an indirect access path to more GPIO capability via PCI Bus accesses
when controlling the GPIO header (J5) connected to the ALi M1535D+ South Bridge.
Please refer to section
"ALi South Bridge Interface, M1535D+, U15"
programming and controlling the ALi M1535D+ GPIO port.
Chapter 2: ML310 Embedded Development Platform
is compatible with the PC IV JTAG programming
GND
GND
GND
GND
13
14
NC
NC
PC4_TDI
device.Table 2-5
shows the JTAG connections from System ACE
System ACE (U38)
80
81
82
85
www.xilinx.com
1-800-255-7778
GND
GND
GND
1
2
VCCV3
PC4_TMS
PC4_TCK
UG000_05_21_082802
XC2VP30 (U37)
G7
F5
F26
H8
for more details on
ML310 User Guide
UG068 (v1.01) August 25, 2004
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