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Table 2-6: User LED Connections (Continued)
CPU Reset Button (10)
The CPU reset button is an active low push button intended to be used as a system or user
reset button. This button is wired to an FPGA I/O pin so it can also be used as a general
purpose button (see
Table 2-7: CPU Reset Connections
Program Switch (11)
When pressed, this switch grounds the Program pin of the FPGA. This clears the FPGA.
JTAG Configuration Port (12)
The JTAG configuration port for the board (J20) allows for device programming and FPGA
debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products.
Third-party configuration products may also be available. The JTAG chain may also be
extended to an expansion board by setting jumper J26 accordingly. See the
Options," page 11
Configuration Options
The FPGA on the SP-305 Development Platform can be configured through JTAG by 2
devices:
•
•
The following section provides an overview of the possible ways the board can be
configured.
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
Reference
Label/Definition
Designator
DS13
LED West
DS12
LED Center
Table
2-7).
Reference
Designator
SW10
FPGA CPU RESET
section for more information.
Parallel Cable IV cable (JTAG)
Platform Flash memory
www.xilinx.com
Color
Green
Green
Label/Definition
Detailed Description
FPGA Pin
F2
H7
FPGA Pin
G2
"Configuration
11
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