Configuration Options - Xilinx KC705 User Manual

Configuration Options

The FPGA on the KC705 board can be configured by the following methods:
•
•
•
See UG470, 7 Series FPGAs Configuration User Guide for details on configuration modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0)
settings selected through DIP switch SW13.
settings.
Table 1-35: Mode Switch SW13 Settings
Figure 1-39
X-Ref Target - Figure 1-39
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
The mode pins settings on SW13 determine if the Linear BPI Flash or the Quad SPI Flash is
used for configuring the FPGA. DIP switch SW13 also provides the upper two address bits
for the Linear BPI Flash and can be used to select one of multiple stored configuration
bitstreams.
devices used for configuration and the FPGA.
To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the
EMCCLK pin of the FPGA. This allows users to create bitstreams that will configure the
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Master BPI (uses the Linear BPI Flash).
Master SPI (uses the Quad-SPI Flash).
JTAG (uses the USB-to-JTAG Bridge or Download cable). See
page 22 for more information
Configuration
Mode Pins (M[2:0])
Mode
Master SPI
Master BPI
JTAG
shows mode switch SW13.
R396 R398
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R397
1.21kΩ
0.1 W
1%
GND
Figure 1-39: Mode Switch
Figure 1-40 shows the connectivity between the onboard non-volatile Flash
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Table 1-35
Bus
Width
x1, x2, x4
001
x8, x16
010
101
VCC2V5
SW13
ON
1
10
9 2
3
8
7 4
5
6
SDA05H1SBD
R400
1.21kΩ
0.1 W
1%
R399
1.21kΩ
0.1 W
1%
Configuration Options
USB JTAG Module,
lists the supported mode switch
CCLK
Direction
Output
Output
x1 Not Applicable
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG810_c1_32_120511
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