Ucf Location Constraints; Creating And Programming Configuration Images For Spi Serial Flash; Spi Flash Prom Programming Options - Xilinx Spartan-3A User Manual

R

UCF Location Constraints

Figure 12-3
pin assignment and the I/O standard used.
Creating and Programming Configuration Images for SPI Serial
Flash
Refer to the "Master SPI Mode" chapter in the Spartan-3 Generation Configuration User Guide
for information on how to create and format FPGA configuration images for SPI serial
Flash and how to program SPI Flash using the Xilinx iMPACT software.
•

SPI Flash PROM Programming Options

Starting with ISE 9.1i, Service Pack 2 and later, the iMPACT programming software
supports two different methods to program an attached SPI Flash PROM, as summarized
in
Using the
the SPI Flash PROM. The FPGA is not involved in the programming process and the FPGA
I/O pins that connect to the PROM must be in their high-impedance state (Hi-Z) during
programming. Hold the FPGA's PROG_B input Low using jumper J16 to place the I/Os in
Hi-Z; the FPGA's DONE pin remains Low.
Using the
JTAG port. The iMPACT software first programs the FPGA with a special design that
performs the SPI PROM programming and uses the JTAG interface as a serial
communications port. During the process, the FPGA's DONE output is High and the
DONE LED is lit because the FPGA is configured with the programming logic. All pins
that are not connected to the SPI Flash PROM or the JTAG interface have an internal
pull-up resistor to the V
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
provides the UCF constraints for the SPI serial Flash PROM, including the I/O
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "AB20" |
NET "SPI_MOSI" LOC = "AB14" |
NET "SPI_SCK" LOC = "AA20" |
NET "SPI_SS_B" LOC = "Y4"
NET "ALT_SS_B" LOC = "Y5"
# write-protect and reset controls for Atmel AT45DB161D PROM
NET "DATAFLASH_WP" LOC
NET "DATAFLASH_RST" LOC
# write-protect control for ST M25P16 PROM
NET "ST_SPI_WP" LOC
Figure 12-3: UCF Location Constraints for SPI Flash Connections
UG332: Spartan-3 Generation Configuration User Guide
www.xilinx.com/bvdocs/userguides/ug332.pdf
Table 12-5.
Direct Programming
Indirect Programming
CCO
www.xilinx.com
IOSTANDARD = LVTTL ;
IOSTANDARD = LVTTL |
IOSTANDARD = LVTTL |
| IOSTANDARD = LVTTL |
| IOSTANDARD = LVTTL |
= "C14" | IOSTANDARD = LVTTL |
= "C15" | IOSTANDARD = LVTTL |
= "C13" | IOSTANDARD = LVTTL |
Method, the programming cable communicates directly to
Method, the programming cable connects to the FPGA's
voltage supply associated with the pin.
UCF Location Constraints
SLEW = SLOW | DRIVE = 4 ;
SLEW = SLOW | DRIVE = 12 ;
SLEW = SLOW | DRIVE = 4 ;
SLEW = SLOW | DRIVE = 4 ;
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
= 4 ;
= 4 ;
= 4 ;
95