Rs-232 Cable Specification - Mitsubishi QJ71C24/-R2 User Manual

3 SPECIFICATIONS

3.2.2 RS-232 cable specification

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REMARK
(1) Confirmation of RS-232 control signal status
The control signal status of DTR, DSR, RS, and CD can be confirmed during
data communication by the RS-232 control signal status storage area (address
254 , 264 ) of the GX Configurator-SC or Q series C24 buffer memory.
H H
Bit position
b0
b1
b2
b3
b4
b5
b6 to b15
1 System area for QJ71C24 (-R2)
(2) Designation of RS and DTR signal status
When the Q series it turned on or off, the on and off states of the RS and DTR
signals can be designated when the buffer memory of the RS and DTR signal
status designation area (address: 92
on or off by the RS signal or DTR signal.
Buffer memory address 92
1 The RS signal is controlled by the Q series C24 in the following cases. (Ignore setting
contents.)
• When data is communicated with half-duplex communication
• When communication time and the RS and CS signals are controlled by the modem function
2 The DTR signal is controlled by the Q series C24 in the following cases. (Ignore setting
contents.)
• When the DTR and DSR signals are controlled
• When data is communicated by the modem function
3 After writing in the buffer memory, a lag of 0 to 20 ms occurs until it is reflected in the signal.
POINT
Be sure to control the RS and DTR signals with the Q series C24. Control of the RS
and DTR signals by the user is a prime factor for data communication errors.
• Use a 15 m (49.21 ft.), or shorter, cable conforming to the RS-232 standard as the
RS-232 cable.
(Recommended cable)
7/0. 127 P HRV-SV... : Designates the number of pairs. (For 13 pairs 7/0.127
13P HRV-SV)
(Oki Electric Cable Co., Ltd)
CH1 side
254
, 132
H
b15
/132
H H
System
Buffer memory address
H
RS
DSR
DTR
CD
1
CS
RI
—
) for the corresponding bit is turned
H
1 2 3
b3 b2 b1 b0
1/0 1/0
MELSEC-Q
CH2 side
264
H
[Default 0005 ]
H
1:ON
RS
0:OFF
DTR
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