APPENDIX
Q02H/Q06H/Q12H/
Q25H/Q12PH/Q25PH
Instruction name
CPU
QJ71C24N
(-R2/R4)
ONDEMAND
48.0
OUTPUT
23.4
PRR
23.3
INPUT
3.4
BIDOUT
28.6
BIDIN
26.4
PUTE
881.9
GETE
1.1
SPBUSY
0.1
CSET
1.0
BUFRCVS
0.3
App. - 16
2) Processing time of dedicated instructions
The following table shows the operation processing time (rough
standard) of each dedicated instruction.
The operation processing time differs slightly depending on the system
configuration and communication protocol.
Processing time (unit: ms)
Q02CPU
QJ71C24
QJ71C24N
QJ71C24
(-R2)
(-R2/R4)
(-R2)
51.5
48.6
52.2
24.8
23.8
25.3
26.8
24.2
27.0
9.9
3.9
9.9
47.0
30.5
47.1
29.1
27.6
29.9
881.9
884.4
884.4
1.1
1.5
1.5
0.1
0.2
0.2
1.2
1.6
1.7
0.3
0.5
0.5
Q00J/Q00/ Q01CPU
Transmission
QJ71C24N
QJ71C24
(-R2/R4)
(-R2)
49.7
53.6
19200 bps
25.6
26.7
Data size: 8
Stop bit: 1
25.1
28.3
Parity: none
4.9
10.0
32.6
49.6
29.8
31.7
871.4
899.5
3.1
3.2
0.3
0.3
3.4
3.9
—
—
19200 bps
MELSEC-Q
Instruction execution condition
Transmission/receive
speed
(registered) data count
40 bytes
40 bytes
40 bytes
8 bytes
5 frames
—
40 bytes
—
40 bytes
—
40 bytes
—
40 bytes
—
40 bytes
—
—
—
—
40 bytes
Others
Send in form 3
—
—
Execute
instruction after
40 bytes have
been received.
—
—
—
—
—
Transmission/
receipt buffer
setting
—
App. - 16