Oki OKIFAX 5950 Series Maintenance Manual page 440

R76-
A3.1.6 CPU Peripheral Circuits
A3.1.6.1 Memory
(1) DRAM
Size: 8 Mbytes (4 megabits x 16 bits; One chip)
Drive voltage: 3.3 V
The basic control signal is generated by the bus state controller incorporated in the CPU.
(2) Flash ROM
Size: 1.5 Mbytes (512K bits x 16 bits + 256K bits x 16 bits; A total of two chips)
A3.1.6.2 Peripheral elements
(1) Clock
A real-time clock IC (serial I/F) incorporating a crystal oscillator is used. Its basic fre-
quency is 500 Hz. CPU pins 110 (RTCTXD), 109 (RTCDATA), and 112 (RTCCLK) are
used as I/F signal pins. The drive voltage is 3 V and backed up by a dedicated lithium
battery.
(2) Speaker drive circuit
A tone switching output board is used to switch between the 2441 Hz waveforms output
from the LSI chip (IOGA5), issuing various buzzer sounds, key touch sound, ringing tone
and line monitor sounds.
A block diagram is shown below.
MCNT-PCB
IOGA5
OF5750/5950 Series January 2001
Attenuator Analog
switch
MOCN2
MOCN1
MOCN0
A3 - 12
CN10
AMP
Speaker
0V