A3.1.3
Scanner Control
A3.1.3.1 Overview
This system uses a monochromic 300-DPI image sensor. It also uses a 1-chip LSI for sensor
control.
The overall block diagram is shown on the next page.
(1) Interface
The IOGA5 receives image data from the sensor control LSI, and sends it to the host
CPU in blocks of 16 bits (2 words).
MDREQ
CPU
MDACKn
Data bus
(16 bit)
(2) Sensor Specifications
Pixel density: 300 DPI
Number of significant pixels: 2552 dots
Pixel clock frequency: 2.5 MHz
The input signal timing chart is shown below.
CLK1
400nS
S1
OF5750/5950 Series January 2001
SDREQ
IOGA5
Sensor control
SDACKn
Data bus
(8 bit)
1.25 ms (line storage time)
A3 - 5
SI
Image sensor
LSI
CLK
R76-