Video Data Output For The A501K/Kc - Basler WOOD BURNING FIREPLACE Wood Burning Fireplace

2.5.7 Video Data Output for the A501k/kc

cameras output the video data in a 2 x 8 Bit data stream.
A501
k/kc
The pixel clock is used to time data sampling and transmission. As shown in Figures
13, the camera samples and transmits data on each rising edge of the pixel clock.
The image has a maximum size of 1280 x 1024 pixels that are transmitted with a Pixel Clock
frequency of 50 MHz over the Channel Link transmitter/receiver pair X. With each clock cycle two
pixels at a depth of 8 Bits are transmitted in parallel. Therefore one line takes a maximum of 640
clock cycles to become transmitted. For more details about sensor timing, refer to the Micron
MV13 data sheet (www.micron.com).
Due to the internal sensor design, the starting columns of areas of interest (AOIs; see section 3.11)
are restricted to values of multiples of 10 + 1. AOI widths, expressed in columns, are restricted to
multiples of 10. For details, read the register description of the AOI Starting Column and the AOI
Width register. Image is transmitted line by line from top left to bottom right. Frame Valid (FVAL)
and Line Valid (LVAL) mark the beginning and duration of frame and line.
The line valid bit indicates that a valid line is being transmitted. Pixel data is valid when the line
valid bit is high.
The sensor outputs 10 Bits, but the two bits output from each ADC are dropped and only 8 bits of
data per pixel is transmitted. The digital shift function selects the bits to be dropped (see section
3.10).
The data sequence outlined below, along with Figures
is happening at the inputs to the Channel Link transmitters in the camera.
Note that the timing used for sampling the data at the Channel Link receivers in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. For specific timing information,
see the data sheet for the receiver that you are using .
Video Data Sequence for the A501k/kc
When the camera is not transmitting valid data, the frame valid and line valid bits sent on each
cycle of the pixel clock will be low. The camera can acquire a frame and, at the same time, send
the previous frame. It can also first acquire a frame and then send it. When Frame valid becomes
high, the camera starts to send valid data:
• On the pixel clock cycle where frame data transmission begins, the frame valid bit will
become high. Five pixel clocks later, the line valid bit will become high (if AOI Starting Col-
umn = 0).
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Two data streams are transmitted in parallel during this clock cycle. The first
pixel is the first pixel in the first data stream D_0. The second pixel is the first pixel in the sec-
ond data stream D_1. 8 bits will contain the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The third pixel is the second
pixel in the D_0 data stream. The fourth pixel is the second pixel in the D_1 data stream. 8
bits will contain the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The fifth pixel is the third
pixel in the D_0 data stream. The sixth pixel is the third pixel in the D_1 data stream. 8 bits
will contain the data for each pixel.
Basler A500
k
PRELIMINARY
Camera Interface
2-12
2-12 and 2-13, describe what
and 2-
2-29