AXIOMTEK SBC81700 Series User Manual page 44

SBC81700 VIA V4 SBC User's Manual
CPU & PCI Bus Control
Use this item to enable the immediate Write to PCI Bus, or disable
it for a later execution. Scroll to this item and press <Enter> to view
the sub menu CPU & PCI Bus Control.
PCI Master 0 WS Write
When this item is enabled, the writes to the PCI bus will be
executed with zero wait state.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Select "Enabled" to
support compliance with PCI specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features page.
System BIOS Cacheable
Use this item to enable or disable the system BIOS cache.
Video RAM Cacheable
Use this item to enable or disable the video RAM cache.
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Phoenix-Award BIOS Utility