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The top-level design file contains top-level verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and I/O standard for each user-defined I/O pin.
Finally, Quartus II programmer must be used to download SOF file to DE2-115 board using JTAG
interface.
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This section provides the detailed procedures on how the DE2-115 System Builder is used.
Install and launch the DE2-115 System Builder
The DE2-115 System Builder is located in the directory:
"DE2_115_tools\DE2_115_system_builder" on the DE2-115 System CD. Users can copy the whole
folder to a host computer without installing the utility. Launch the DE2-115 System Builder by
executing the DE2_115_SystemBuilder.exe on the host computer and the GUI window will appear
as shown in
Figure
5-2.
Start
Launch
DE2-115 System Builder
Create New
DE2-115 System Builder
Project
Generate
Quartus II Project
and Document
.QPF
.QSF
.V
.HTM
.SDC
Figure 5-1 The general design flow of building a design
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Launch Quartus II and
Open Project
Add User Design/Logic
Compile to generate
Configure FPGA
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.SOF
End
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