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After the IR receiver on DE2-115 board receives this frame, it will directly transmit that to FPGA.
In this demo, the IP of IR receiver controller is implemented in the FPGA. As
Figure 6-20
shows, it
includes Code Detector, State Machine, and Shift Register. First, the IR receiver demodulates the
signal inputs to Code Detector block .The Code Detector block will check the Lead Code and
feedback the examination result to State Machine block.
The State Machine block will change the state from IDLE to GUIDANCE once the Lead code is
detected. Once the Code Detector has detected the Custom Code status, the current state will change
from GUIDANCE to DATAREAD state. At this state, the Code Detector will save the Custom Code
and Key/Inv Key Code and output to Shift Register then displays it on 7-segment displays.
Figure
6-21
shows the state shift diagram of State Machine block. Note that the input clock should be
50MHz.
Figure 6-20 The IR Receiver controller
Figure 6-21 State shift diagram of State Machine
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