Altera DE2-115 User Manual page 91

Figure 6-13 shows the hardware block diagram of this demonstration. The system requires a 50
MHz clock provided from the board. The PLL generates a 100MHz clock for Nios II processor and
the other controllers except for the audio controller. The audio chip is controlled by the Audio
Controller which is a user-defined SOPC component. This audio controller needs an input clock of
18.432 MHz. In this design, the clock is provided by the PLL block. The audio controller requires
the audio chip working in master mode, so the serial bit (BCK) and the left/right channel clock
(LRCK) are provided by the audio chip. The 7-segment display is controlled by the SEG7
Controller which also is a user-defined SOPC component. Two PIO pins are connected to the I2C
bus. The I2C protocol is implemented by software. Four PIO pins are connected to the SD Card
socket. The IR receiver is controlled by the IR Controller which also is a user-defined SOPC
component. SD 4-Bit Mode is used to access the SD Card and is implemented by software. All of
the other SOPC components in the block diagram are SOPC Builder built-in components.
Figure 6-13 Block diagram of the SD music player demonstration
Figure 6-14 shows the software stack of this demonstration. SD 4-Bit Mode block implements the
SD 4-Bit mode protocol for reading raw data from the SD Card. The FAT block implements
FAT16/FAT32 file system for reading wave files that is stored in the SD Card. In this block, only
read function is implemented. The WAVE Lib block implements WAVE file decoding function for
extracting audio data from wave files. The I2C block implements I2C protocol for configuring
audio chip. The SEG7 block implements displaying function to display elapsed playing time. The
Audio block implements audio FIFO checking function and audio signal sending/receiving function.
The IR block acts as a control interface of the music player system.
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