Using The 7-Segment Displays - Altera DE2-115 User Manual

LEDR[15] PIN_G15
LEDR[16] PIN_G16
LEDR[17] PIN_H15
LEDG[0] PIN_E21
LEDG[1] PIN_E22
LEDG[2] PIN_E25
LEDG[3] PIN_E24
LEDG[4] PIN_H21
LEDG[5] PIN_G20
LEDG[6] PIN_G22
LEDG[7] PIN_G21
LEDG[8] PIN_F17
4 . 4 U s i n g t h
4 . 4 U s i n g t h
The DE2-115 Board has eight 7-segment displays. These displays are arranged into two pairs and a
group of four, behaving the intent of displaying numbers of various sizes. As indicated in the
schematic in Figure
IV E FPGA. Applying a low logic level to a segment will light it up and applying a high logic level
turns it off.
Each segment in a display is identified by an index from 0 to 6, with the positions given in
4-10. Table 4-4 shows the assignments of FPGA pins to the 7-segment displays.
Figure 4-10 Connections between the 7-segment display HEX0 and Cyclone IV E FPGA
Signal Name
HEX0[0]
HEX0[1]
HEX0[2]
HEX0[3]
HEX0[4]
e 7 - s e g m e n
e 7 - s e g m e n
4-10, the seven segments (common anode) are connected to pins on Cyclone
Table 4-4 Pin Assignments for 7-segment Displays
FPGA Pin No. Description
PIN_G18 Seven Segment Digit 0[0]
PIN_F22 Seven Segment Digit 0[1]
PIN_E17 Seven Segment Digit 0[2]
PIN_L26 Seven Segment Digit 0[3]
PIN_L25 Seven Segment Digit 0[4]
LED Red[15]
LED Red[16]
LED Red[17]
LED Green[0]
LED Green[1]
LED Green[2]
LED Green[3]
LED Green[4]
LED Green[5]
LED Green[6]
LED Green[7]
LED Green[8]
t D i s p l a y s
t D i s p l a y s
36
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
I/O Standard
2.5V
2.5V
2.5V
Depending on JP7
Depending on JP7
Figure