Asynchronous Communications (Camera Link) Interface; Definition Of The Transfer Protocol - Dalsa 1M28-SA User Manual

1M28, 1M75, and 1M150 User's Manual
Asynchronous Communications Asynchronous Communications Asynchronous Communications Asynchronous Communications
(Camera Link) Interface (Camera Link
(Camera Link (Camera Link
The asynchronous communications serial communicator interface is part of Camera Link. (Refer to
the Camera Link Specification for more information). This interface is often used in industrial
image processing for controlling camera settings. The following communication settings from the
asynchronous serial communications protocol have been chosen for the 1MXXX camera series:
Baud rate
Startbit
data bits
Parity
Stopbit
In the idle state the leads RX and TX are characterised by a standard H-level. Data transfer begins
with a startbit, which has an L-level. Next, the 8 data bits are transmitted in the sequence from
D0...D7. The parity bit follows the data. In order to separate subsequent data, a stop bit of H-level
is added. The total number of cycles necessary for data transfer is 11. After the data transfer,
signals return to the idle state.

Definition of the Transfer Protocol

Due to the 8-bit RS232 limitation, it is not possible to distinguish between data and address
transfers. The protocol in Table 28 is implemented to allow access to the 64 internal camera
registers.
Table 28: Communications Protocol
RS232 Communication
Protocol
Command to camera
controller
WRITE Address
WRITE Data Low Nibble
WRITE Data High Nibble
READ Data of Addresses
x:
Ai: Address bits
Dj: Data bits
When data or addresses are written (WRITE Mode), the RS232 interface of the camera answers
with ACK = 06H if the transfer was successful, or with NAK = 15H if the transfer failed.
Therefore, it is possible to control the complete transfer process by the software. When a register is
DALSA
PRELIMINARY
9600
1
8
None
1
don't care
Appendix B Appendix B Appendix B Appendix B
) Interface
) Interface ) Interface
Data bits
7 6 5 4
0 1 A5 A4
1 0 x x
1 1 x x
0 0 A5 A4
3 2 1 0
A3 A2 A1 A0
D3 D2 D1 D0
D7 D6 D5 D4
A3 A2 A1 A0
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