Dalsa 1M28-SA User Manual page 71

1M28, 1M75, and 1M150 User's Manual
Figure 32: Captured picture with active 10bit LFSR
References:
[SMITH00] Douglas J. Smith, "HDL Chip Design", 7. Auflage 2000 Doone Publications,
Madison, AL, S. 179 - 186
ISBN 0-9651934-3-8
Example: VHDL Code
signal REG: STD_LOGIC_VECTOR (9 downto 0);
signal DATAIN: STD_LOGIC;
SR10R: process (ICLK)
begin
with 1.
end process SR10R;
DATAIN
LFSR_OUT <= REG;
DALSA
PRELIMINARY
if (ICLK'event and ICLK='1') then
if (RESET = '1') then
REG <= "0000000001";
else
REG <= REG(8 downto 0) & DATAIN;
end if;
end if;
<= REG(2) xor REG(9);
-- 10 bit LFSR
-- reset:shift register is loaded
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