Mitsubishi Electric MELSEC Q Series User Manual page 186

(c) Memory configuration of multiple CPU high speed transmission area
1) Addresses of user setting area
The addresses of user setting area depend on the CPU module.
For user setting area addresses, refer to Section 4.1.1.
2) Addresses of multiple CPU high speed transmission area
The following explains the memory configuration of the multiple CPU high speed transmission area that is
used in the multiple CPU high speed transmission function. (For the CPU shared memory, refer to Section
4.1.1.)
Multiple CPU high
speed transmission area
*1:Indicates addresses when user setting area for each CPU is specified using multiple CPU devices.
Figure 4.42 Memory configuration of multiple CPU high speed transmission area
For the each area of the multiple CPU high speed transmission area, refer to Section 4.1.3.
(2) Parameter setting
When performing the auto refresh of the multiple CPU high speed transmission area, the number of points to be
sent by each CPU module is set in the PLC parameter "Multiple CPU settings."
For the setting description of the parameter, refer to Section
High
Note4.9 Process
performance
For the High Performance model QCPU, Process CPU, Basic model QCPU, Universal model QCPU(Q00UCPU,
Q01UCPU, Q02UCPU), parameter setting can be ignored since the user setting area of the multiple CPU high speed
transmission area is not available.
*1
U3E0\G10000
CPU No.1 send range
to
*1
U3E1\G10000
CPU No.2 send range
to
*1
U3E2\G10000
CPU No.3 send range
to
*1
U3E3\G10000
to CPU No.4 send range
Note4.9
Basic
Universal
CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES
4.1.3.íç1
User setting area
Auto refresh area
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