Table of Contents
Advertisement
TDM Interface:
FRAMER ANALOG INTERFACES
The Pm8560 routes channels out the backplane through the rear transition module (RTM)
providing protection circuitry which protects equipment from overvoltage and overcurrent
stresses from lightning strikes, power crosses and other noise impairments. This circuitry is
necessary in cases where the connections are outside the customer's building, and in some
cases within the same building (depending on the application).
The requirements for T1 equipment are specified by FCC Part 68 (lightning), UL1950 (AC
Hazards), Bell Core TR-TSY-000007 and AT&T Publication 62411. Similar requirements are
specified for E1 equipment including ETS 300 0460-3 and ITU K17 through K20. Additional
magnetics and protection devices are located on the transition modules.
Note:
To ensure compliance with these standards, it will be necessary to undergo appropriate testing at an
approved lab.
FRAMER TO MPC8560 INTERFACE
This interface uses the clock and sync registers (starting on page 8-12) for system configu-
ration. Specific configurations also use the MT9045 System Synchronizer device. Setting up
the MT9045 in the desired mode and frequency requires two steps:
1
Drive the correct Pm8560 CPM port pins (PC5, PC6, PC7, PC12, PC13) as defined in
Table 3-3
2
Set the appropriate registers in the MT9045 System Synchronizer Control register (SSCR)
on page 8-15.
3
Whenever any of the MT9045 control inputs are changed, assert the reset to the MT9045.
See the "Reset Command (RCR), 0x24" on page 8-7.
Interface Options
There are line and system interface options. Line refers to the external T1/E1 connections to
the Pm8560, system is the internal databus speed between the Pm8560 processor and
framer.
tor and MT9045 options. For a more detailed diagram of the clock and sync registers, see
Fig. 8-2
ples are listed below:
T1/J1 E1 line, T1/J1 E1 system:
• T1/J1 E1 line is either 1.544 MHz or 2.048 MHz
• T1/J1 E1 system is either 1.544 MHz or 2.048 MHz
• MT9045 generates TCLK, TSYNC, RCLK, and RSYNC
6-2
Pm8560 User's Manual
Framer Analog Interfaces
.
illustrates the framer to processor data flow including both the 2.048 oscilla-
Fig. 6-1
. There are a number of possible framer to processor interface options, three exam-
10006609-03
Advertisement
Table of Contents
Troubleshooting
