P4 Jtag Chain Header; Table 10-5: Dmc P4 Jtag Header Pin Assignments - Emerson Pm8560 User Manual

Octal e1/t1/j1 line interface ptmc

Table of Contents

Development Mezzanine Card:

CPU_CKSTP_OUT*:

DEBUG_HRESET*:

DEBUG_SRESET*:

DEBUG_TRST*:

CPU_TCK:

CPU_TDI:

CPU_TDO:

CPU_TMS:

Figure 10-5:

Table 10-5:

CPLD_TCK:

10-6

Pm8560 User's Manual

Pin:

Signal:

CPU_TCK

CPU_TMS

DEBUG_SRESET*

DEBUG_HRESET*

CPU_CKSTP_OUT*

Checkstop Output—when asserted, this output signal indicates that the CPU has detected a

checkstop condition and has ceased operation.

Hard Reset—this input signal indicates that a complete Power-on Reset must be initiated by

the processor.

Soft Reset—this input signal indicates that the MPC8560 must initiate a System Reset inter-

rupt.

Test Reset—this input signal resets the test access port.

Test Clock Input—scan data is latched at the rising edge of this signal.

Test Data Input—this signal acts as the input port for scan instructions and data.

Test Data Output—this signal acts as the output port for scan instructions and data.

Test Mode Select—this input signal is the test access port (TAP) controller mode signal.