Double Data Rate Sdram; Ddr Sdram Programming - Emerson Pm8560 User Manual

On-Card Memory:

DOUBLE DATA RATE SDRAM

The Pm8560 supports up to 512 megabytes of DDR SDRAM for data storage. On-card
SDRAM occupies physical addresses starting at 0000,0000
tecture is designed to enhance performance especially in high-speed operation. The DDR
SDRAM interface operates at 133 MHz when the processor core is at 800 MHz.
The SDRAM is controlled by the MPC8560 SDRAM controller, see
may be programmed for most memory sizes through software initialization of the on-chip
configuration registers. Software determines the board's capacity by reading the Hardware
Configuration register 1, see page 8-4. The DDR memory controller supports Error-correct-
ing Code (ECC) by detecting and correcting all single-bit errors, and detects all double-bit
errors and all errors within a nibble.
Figure 4-1: MPC8560 To SDRAM Connection

DDR SDRAM Programming

After power-up, the DDR SDRAM must be initialized by issuing a Mode register set com-
mand to establish its mode of operation. During that command execution, data is read by
the Mode register from the SDRAM's address bus. This command is fully supported by the
MPC8560 DDR SDRAM machine.
Table 4-2: DDR SDRAM Mode Register Definition
Address Bus (bits):
BA1-BA0 (14:13)
Double Data Rate SDRAM
Mode Field:
Base Mode
10006609-03
. The double data rate archi-
16
Fig. 4-1
Value: Description:
'0,0' Selects Base Mode register
Pm8560 User's Manual
. The controller
4-3