Baud Rate Selection; Baud Rate Generator Configuration - Emerson Pm8560 User Manual

Octal e1/t1/j1 line interface ptmc
Table of Contents

Advertisement

Serial I/O:

Baud Rate Selection

Table 5-3:
Baud Rates for 33 MHz and 66 MHz Clocks
Baud Rate:
2400
4800
9600
14400
19200
38400
57600
115200

Baud Rate Generator Configuration

The Baud Rate Generator Configuration (BRGCx) registers can be written at any time with
no need to disable the SMCs or external devices that are connected to the BRG. Configura-
tion changes occur at the end of the next BRG clock cycle. Although the BRGC can be
changed on-the-fly, two changes should not occur within a time equal to two source clock
periods. BRGC5-8 registers start at physical address space FDF9,15F0
ters start at physical address space FDF9,19F0
registers, refer to the MPC8560 PowerQuicc III Integrated Communications Processor Reference
Manual.
BRG Clock Divider Value
Decimal:
1
3472
1736
868
579
434
217
145
72
1. The EIA-232C specification defines a maximum rate of 20,000 bits per second over a typical 50-foot
cable (2,500 picofarads maximum load capacitance). Higher baud rates are possible, but successful
operation depends specifically upon the application, cable length, and overall signal quality
10006609-03
Hex:
Actual Frequency (Hz):
D90
2399
6C8
4797
364
9589
243
14375
1B2
19156
0D9
38224
091
57205
048
113629
. For more detailed information on these
16
% Error:
.03
.06
.12
.17
.23
.46
.69
1.36
and BRGC1-4 regis-
16
5-3
Pm8560 User's Manual

Advertisement

Table of Contents
loading

Table of Contents