Ct Bus Status; Clock And Sync Registers - Emerson Pm8560 User Manual

Programmable Logic Device:
I2CSDA:
I2CSCL:
Register 8-14:
reserved:
PTEN:
CTEN:
8-12
Pm8560 User's Manual
2
I C Data line
0 Drive a 0 onto the I2C SDA line
1 Drive a 1 onto the I2C SDA line
2
I C Clock line
0 Drive a 0 onto the I2C SCL line
1 Drive a 1 onto the I2C SCL line

CT Bus Status

The CTSR connects or isolates the CT NETREF, C8A, C8B, and connector P13 SIO connec-
tions.
CT Bus Status (CTSR), 0x38
7 6
Default is 000000
Signal PTENB* on connector P13, pin 39 (read only)
0 PTENB inactive
1 PTENB active (default on reset)
CT bus connection (read/write)
0 CT bus isolated
1 CT bus connected

CLOCK AND SYNC REGISTERS

is a detailed diagram of the clock and sync registers 0x40 through 0x5c. This dia-
Fig. 8-2
gram is a tool designed to help configure the TDM interfaces. Refer to the specific CPLD
register for more detail.
Clock and Sync Registers
5 4 3
reserved
10006609-03
2 1 0
PTEN CTEN