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2.13
Memory Thermal Control
2.13.1
MC_THERMAL_CONTROL0
MC_THERMAL_CONTROL1
MC_THERMAL_CONTROL2
Controls for the Integrated Memory Controller thermal throttle logic for each channel.
Device:
Function: 3
Offset:
Access as a Dword
Bit
2
1:0
2.13.2
MC_THERMAL_STATUS0
MC_THERMAL_STATUS1
MC_THERMAL_STATUS2
Status registers for the thermal throttling logic for each channel.
Device:
Function: 3
Offset:
Access as a Dword
Bit
29:4
3:0
92
4, 5, 6
48h
Reset
Type
Value
APPLY_SAFE.
RW
1
Enable the application of safe values while
MC_THERMAL_PARAMS_B.SAFE_INTERVAL is exceeded.
THROTTLE_MODE. S
elects throttling mode.
00 = Throttle disabled
01 = Open Loop: Throttle when Virtual Temperature is greater than
RW
0
MC_THROTTLE_OFFSET.
10 = Closed Loop: Throttle when MC_CLOSED_LOOP.THROTTLE_NOW is set.
11 = Closed Loop: Throttle when MC_DDR_THERM_COMMAND.THROTTLE is set
and the MC_DDR_THERM pin is asserted OR OLTT will be implemented
(Condition 1).
4, 5, 6
4Ch
Reset
Type
Value
CYCLES_THROTTLED.
RO
0
The number of throttle cycles, in increments of 256 Dclks, triggered in any rank
in the last SAFE_INTERVAL number of ZQs.
RANK_TEMP.
RO
0
The bit specifies whether the rank is above throttling threshold.
Register Description
Description
Description
Datasheet
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