Condition Bit Register: Cbr (Cr1); Interrupt Stack Pointer: Spi (Cr2); User Stack Pointer: Spu (Cr3); Backup Pc: Bpc (Cr6) - Renesas M32R-FPU Software Manual

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1.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its
Condition (C) bit. The value written to the PSW register's C bit is reflected in this
register. The register can only be read. (Writing to the register with the MVTC
instruction is ignored.)
At reset release, the value of CBR is "H'0000 0000".
b0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C
CBR

1.3.3 Interrupt Stack Pointer: SPI (CR2)

User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the
address of the current stack pointer. These registers can be accessed as the
general-purpose register R15. R15 switches between representing the SPI and
SPU depending on the value of the Stack Mode (SM) bit in the PSW.
At reset release, the value of the SPI and SPU are undefined.
b0
SPI
b0
SPU

1.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when
an EIT occurs. Bit 31 is fixed to "0".
When an EIT occurs, the register sets either the PC value when the EIT occurred or
the PC value for the next instruction depending on the type of EIT. The BPC value
is loaded to the PC when the RTE instruction is executed. However, the values of
the lower 2 bits of the PC are always "00" when returned (PC always returns to the
word-aligned address).
At reset release, the value of the BPC is undefined.
b0
BPC
CPU PROGRAMMING MODEL
SPI
SPU
BPC
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M32R-FPU Software Manual (Rev.1.01)
1.3 Control Registers
b31
b31
b31
b31
0