Appendix 6.2 Rules Concerning Generation Of Qnan In M32R-Fpu - Renesas M32R-FPU Software Manual

APPENDICES

Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU

T h e f o l l o w i n g a r e r u l e s c o n c e r n i n g g e n e r a t i n g a Q N a N a s a n o p e r a t i o n r e s u l t .
Instructions that generate NaNs as operation results are FADD, FSUB, FMUL, FDIV,
FMADD, and FMSUB.
[Important Note]
This rule does not apply when the data that is sent to Rdest, the results of the FCMP or
FCMPE comparison, comprise a NaN bit pattern.
<FADD, FSUB, FMUL, FDIV>
Source Operand (Rsrc1, Rsrc2)
SNaN and QNaN
Both SNaN
Both QNaN
SNaN and actual number
QNaN and actual number
Neither operand is NaN; IVLD occurs
Note 1: SNaN b9 is set to "1" and the operand is converted to QNaN.
<FMADD, FMSUB>
Source Operand
Rdest
Actual number SNaN and QNaN
Both SNaN
Both QNaN
SNaN and actual number
QNaN and actual number
Neither operand is NaN; IVLD occurs
QNaN Don't care
SNaN Don't care
Note 1: SNaN b9 is set to "1" and the operand is converted to QNaN.
Appendix 6 M32R-FPU Specification Supplemental Explanation
SNaN converted to QNaN (Note 1)
Rsrc2 converted to QNaN (Note 1)
Rscr2
SNaN converted to QNaN (Note 1)
QNaN
H'7FFF FFFF
Rsrc1, Rsrc2
APPENDICES-28
Rdest
Rdest
SNaN converted to QNaN (Note 1)
Rsrc2 converted to QNaN (Note 1)
Rscr2
SNaN converted to QNaN (Note 1)
QNaN
H'7FFF FFFF
Rdest (maintained)
Rdest converted to QNaN (Note 1)
M32R-FPU Software Manual (Rev.1.01)
APPENDIX 6