Appendix 3.2 Pipeline Basic Operation - Renesas M32R-FPU Software Manual

APPENDICES

Appendix 3.2 Pipeline Basic Operation

(1) Pipeline Flow with no Stall
The following diagram shows an ideal pipeline flow that has no stall and executes each
instruction in 1 clock cycle. (Since this is just an ideal case, all instructions may not be
piplined in.)
<Case 1> Integer instructions (register-to-register) are executed continuously
LDI R0,#1
ADD R0,R1
OR R0,R2
CMP R0,R3
<Case 2> Load/store instructions to destination are accessed in 1 cycle continuously
ST R0,@-R15
ST R1,@-R15
LD R2,@R15+
LD R3,@R15+
<Case 3> Register-register instructions are executed with no register dependency following
a load/store instruction (out-of-order-completion)
LD R0,@R2
LDI R1,#1
ADD R1,R3
OR R1,R4
Appendix Figure 3.2.1 Pipeline Flow with no Stall (1)
IF D E WB
IF D E
IF D
IF
* A multi-cycle instruction, such as multiply or divide, executes
multiple cycles in the E stage.
IF D E MEM1 MEM2
IF D E
IF D
IF
IF D E MEM1 MEM1 MEM2
IF D E
IF D
IF
* A multi-cycle instruction, such as multiply or divide, executes multiple
cycles in the E stage.
APPENDICES-10
Appendix 3 Pipeline Processing
WB
E WB
D E WB
WB
MEM1 MEM2 WB
E MEM1 MEM2 WB
D E MEM1 MEM2
WB
WB
E WB
D E WB
M32R-FPU Software Manual (Rev.1.01)
APPENDIX 3
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