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APPENDICES
Appendix 3 Pipeline Processing
Appendix 3.1 Instructions and Pipeline Processing
Appendix Figure 3.1.1 shows each instruction type and the pipeline process.
Load/Store instruction
Pipeline Stage
All other integer instructions
Pipeline Stage
Pipeline Stage
FPU instruction (excluding FMADD, FMSUB)
Pipeline Stage
FPU instruction (FMADD, FMSUB)
Pipeline Stage
*Operation stages with the same name cannot be executed at the same time. In general, stages with
different names can be executed in parallel, but the following combinations are not acceptable.
¥ E stage executed with E1, E2, EM or EA stage.
¥ E1 stage executed with EM or EA stage.
*Bypass process: When using the result of one instruction in a subsequent instruction, the first result
may bypass the register file and be sent on to the execution stage of the subsequent instruction.
The following is an example of a bypass process:
¥ E stage continuing to WB stage
¥ MEM2 stage continuing to WB stage
Appendix Figure 3.1.1 Instructions and Pipeline Process
6 stages
IF
D
E
MEM1
*The number of cycles required by the MEM1 stage varies according to the access,
but the MEM2 stage is normally executed in 1 cycle.
4 stages
IF
D
E
WB
*Multi-cycle instructions such as the multiply instruction are executed in multiple
cycles in the E stage.
¥¥¥¥¥¥
IF
D
E
5 stages
IF
D
E1
E2
*The E1 and E2 stages cannot be executed at the same time as the E stage.
*The E1 stage of the FDIV instruction requires 14 cycles.
6 stages
IF
D
EM
EA
* The EM and EA stages cannot be executed at the same time as the E or E1 stage.
E, E1, EM stages
E, E1, EM, EA stages
APPENDICES-8
Appendix 3 Pipeline Processing
MEM2
WB
E
WB
WB
E2
WB
M32R-FPU Software Manual (Rev.1.01)
APPENDIX 3
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