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APPENDICES
Appendix 4 Instruction Execution Time
Normally, the E stage is considered as representing as the instruction execution time,
however, because of the pipeline processing the execution time for other stages may
effect the total instruction execution time. In particular, the IF, D, and E stages of the
subsequent instruction must be considered after a branch has occurred.
The following shows the number of the instruction execution cycles for each pipeline
stage.
The execution time of the IF and MEM stages depends on the implementation of each
product of the M32R family.
Refer to the user's manual of each product for the execution time of these stages.
Note 1: FPU instruction uses E1 and EM stages.
Appendix Table 4.1.1 Instruction Execution Cycles per Pipeline Stage [excluding FPU instructions]
instruction
load instruction (LD, LDB, LDUB, LDH, LDUH, LOCK)
store instruction (ST, STB, STH, UNLOCK)
BSET, BCLR instructions
multiply instruction (MUL)
divide/reminder instruction (DIV, DIVU, REM, REMU)
other instructions (DSP function instructions,
including BTST, SETPSW, CLRPSW)
Note 1: R, W: Refer to the user's manual prepared for each product.
Note 2: Within the store instruction, only instructions which include the register indirect and
register update addressing mode require 1 cycle in the WB stage. All other instructions
do not require extra cycles.
Appendix Table 4.1.2 Instruction Execution Cycles per Pipeline Stage [FPU instructions]
instruction
FMADD, FMSUB instructions
FDIV instruction
other FPU instructions
Note 1: R, W: Refer to the user's manual prepared for each product.
Appendix 4 Instruction Execution Time
the number of execution cycles in each stage
IF
D
R (note 1) 1
R (note 1) 1
R (note 1) 1 R (note 1) W (note 1)
R (note 1) 1
R (note 1) 1
R (note 1) 1
the number of execution cycles in each stage
IF
D
E1
R (note 1) 1
R (note 1) 1
14
R (note 1) 1
APPENDICES-17
M32R-FPU Software Manual (Rev.1.01)
APPENDIX 4
E
MEM1 MEM2
1
R (note 1)
1
1
W (note 1)
1 (1) (note 2)
1
+3
3
-
-
-
-
37
1
-
-
EM
EA
E2
-
1
1
1
-
-
1
1
-
-
1
WB
1
-
1
1
1
WB
1
1
1
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