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Appendix 6 M32R-Fpu Specification Supplemental Explanation; Appendix 6.1.1 Rounding Mode; Appendix 6.1.2 Exception Occurring In Step 1 - Renesas M32R-FPU Software Manual

32-bit risc single-chip microcomputer

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APPENDICES

Appendix 6 M32R-FPU Specification Supplemental Explanation

Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two
instructions (FMUL and FADD)
The following is an explanation of the differences between an operation using just one
instruction (FMADD or FMSUB) and an operation using 2 instructions (FMUL and
FADD).

Appendix 6.1.1 Rounding Mode

The rounding mode for an operation using both FMUL and FADD rounds both FMUL
and FADD according to the setting of the FPSR RM field. However, the result of the
FMADD or FMSUB instruction in Step 1 (multiply stage) is not rounded according to
the setting of FPSR RM field, rather it is rounded toward zero.

Appendix 6.1.2 Exception occurring in Step 1

Two instructions are compared below as examples of Exception occurring in Step 1.
FMUL + FADD:
FMUL
FADD
FMADD or FMSUB:
FMADD
Note: If the register supports different operations than those described above, the
operations may differ in some ways to those shown below.
Appendix 6 M32R-FPU Specification Supplemental Explanation
R3, R1, R2
(R3 = R1 * R2)
R0, R3, R0
(R0 = R3 + R0)
R0, R1, R2
(R0 = R0 +R1 * R2)
APPENDICES-23
APPENDIX 6
M32R-FPU Software Manual (Rev.1.01)

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