Toshiba TMP92CM22FG TLCS-900/H1 Series Manual page 215

3.12.3 Control Registers
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
1. Setting the detection time for the watchdog timer in <WDTP1:0>
This 2-bit register is used for setting the watchdog timer interrupt time used
when detecting runaway.
On a reset this register is initialized to WDMOD<WDTP1:0> = 00.
The detection time for WDT is 2
approximately 65, 536.)
2. Watchdog timer enable/disable control register <WDTE>
At reset, the WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the
disable code (B1H) to the watchdog timer control register (WDCR). This makes it
difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting <WDTE> to 1.
3. Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD<RESCR> is initialized to 0 at reset, a
reset by the watchdog timer will not be performed.
(2) Watchdog timer control register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
• Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
writing the disable code (B1H) to the WDCR register.
WDCR
WDMOD
WDCR
• Enable control
Set WDMOD<WDTE> to 1.
• Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code
(4EH) to the WDCR register.
WDCR
Note1: If the disable control, set the disable code (B1H) to WDCR after weirint the clear code (4EH) once. (Please
refer to setting example.)
Note2: If the Watchdog timer setting, change setting after setting to disable condition once.
←
0 1 0 0 1 1 1
← 0 − − − − −
0
← 1
0 1 1 0 0 0
← 0
1 0 0 1 1 1
92CM22-213
/f [s]. (The number of system clocks is
15
SYS
0 Write the clear code (4EH).
0 Clear WDMOD <WDTE> to 0.
1 Write the disable code (B1H).
0 Write the clear code (4EH).
TMP92CM22
2007-02-16