Toshiba TMP92CM22FG TLCS-900/H1 Series Manual page 131

TB1MOD Bit symbol
(1192H)
Read/Write
After reset
Function TB1FF1 Inversion trigger
Read-modify
-write
0: Trigger disable
instruction is
1: Trigger enable
prohibited
Invert when
UC12 is
loaded into
TB1CP1H/L
TMRB1 Mode Register
7 6
TB1CT1 TB1ET1 TB1CP0I
R/W
0 0
Software
capture
control
0: Software
Invert when
capture
UC12
1: Undefined
matches
with
TB1RG1H/L
Figure 3.8.5 Register for TMRB
92CM22-129
5 4 3
TB1CPM1 TB1CPM0
W
1 0 0
Capture timing
00: Disable
INT4 is rising edge
01: TB1N0 ↑ TB1IN1 ↑
INT4 is falling edge
10: TB1IN0 ↑ TB1IN0 ↓
INT4 is falling edge
11: TA1TRG ↑
TA1TRG ↓
INT4 is rising edge
Input clock
00 TB1IN0 pin input
01 φT1
10 φT4
11 φT16
Clear up counter (UC12)
0 Clear disable
1 Clear by matching with TB1RG1H/L
Capture/interrupt timing
Capture control
00 Capture disable
01
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at rising edge of TB1IN1
10
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN1
11
Capture to TB1CP0H/L at rising edge of TA1OUT
Capture to TB1CP1H/L at falling edge of TA1OUT
Software capture
0 Capture value of up counter to TB1CP0H/L
1 Undefined
TMP92CM22
2 1
TB1CLE TB1CLK1 TB1CLK0
R/W
0 0
Up counter TMRB1 source clock
control
00: TB1IN0 pin input
01: φT1
0: Clear
10: φT4
disable
11: φT16
1: Clear
enable
INT4 control
Generate INT4
by TB1IN0
rising
Generate INT4
by TB1IN0
falling
Generate INT4
by TB1IN0
rising
2007-02-16
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