Toshiba TMP92CM22FG TLCS-900/H1 Series Manual page 19

3.3.4 Clock Doubler (PLL)
PLL outputs the f
PLL to stop status, setting to PLLCR register is needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lockup time.
Note 1: Input frequency limitation for PLL
The limitation of input frequency (High-frequency oscillation) for PLL is the following.
f
OSCH
Note 2: PLLCR<LWUPFG>
The logic of PLLCR<LUPFG> is different from 900/L1's DFM.
Be careful to judge an end of lockup time.
The following is a setting example for PLL starting and PLL stopping.
Example 1: PLL starting
PLLCR
LUP:
X: Don't care
<PLLON>
<FCSEL>
PLL output: f
PLL
Lockup timer
<LWUPFG>
System clock f
SYS
clock signal, which is four times as fast as f
PLL
= 4 to 10 MHz (Vcc = 3.0 V to 3.6 V)
EQU 10E8H
LD (PLLCR), 10XXXXXXXB
BIT 5, (PLLCR)
JR Z, LUP
LD (PLLCR), 11XXXXXXB
Count-up by f
During lockup
Starts PLL operation and
starts lockup.
92CM22-17
; Enables PLL operation and starts lockup.
;
Detects end of lockup.
;
; Changes fc from 10 MHz to 40 MHz.
OSCH
Changes from 10 MHz to 40 MHz.
Ends of lockup
TMP92CM22
. A reset initializes
OSCH
After lockup
2007-02-16