Table of Contents
Advertisement
φT0
2
4 8 16 32
φT2
Serial clock generation circuit
BR1CR<BR1CK1:0>
φT0
φT2
φT8
φT32
f
io
SCLK1 input
(Shared
with PF5)
I/O interface mode
SCLK1 output
(Shared
with PF5)
Receive control
(UART only ÷ 16)
RXDCLK
Receive buffer
SC1MOD0
<RXE>
Receive buffer 1 (Shift register)
RXD1
(Shared
with PF4)
RB8
Prescaler
64
φT8
φT32
BR1CR
BR1ADD
<BR1S3:0>
<BR1K3:0>
BR1CR
<BR1ADDE>
Baud rate generater
SC1MOD0
<WU>
Receive buffer 2 (SC1BUF)
<OERR> <PERR> <FERR>
Figure 3.9.3 Block Diagram of SIO1
TA0TRG
(from TMRA0)
UART
mode
SC1MOD0
<SC1:0>
SC1MOD0
<SM1:0>
÷ 2
I/O interface mode
SC1CR
<IOC>
Serial channel
interrupt control
TXDCLK
SC1CR
<PE>
<EVEN>
Parity control
Error flag
SC1CR
Internal data bus
92CM22-144
TMP92CM22
SIOCLK
Transmission
counter
(UART only ÷ 16)
Transmission
control
SC1MOD0
<CTSE>
Transmission buffer
TB8
(SC1BUF)
Interrupt request
INTRX1
INTTX1
CTS1
(Shared
with PF5)
TXD1
(Shared
with PF3)
2007-02-16
Advertisement
Table of Contents
