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In this mode, a programmable square wave is generated by inverting the timer output
each time the 8-bit up counter (UC0) matches the value in one of the timer registers
TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>
should be set to "1", so that UC1 is set for counting.
Figure 3.7.14 shows a block diagram representing this mode.
TA0IN
φT1
φT4
φT16
TA01MOD<TA0CLK1:0>
Selector
TA0REG-WR
TA01RUN<TA0RDE>
If the TA0REG double buffer is enabled in this mode, the value of the register buffer will
be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is varied).
Match with TA0REG
and UC0
Match withTA1REG
TA0REG (Value of compare)
Register buffer
Selector
8-bit
up counter
(UC0)
Comparator
TA0REG
Shift trigger
Register buffer
Internal data bus
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
(Up counter = Q
2
Q
1
Figure 3.7.15 Operation of Register Buffer
92CM22-115
TA01RUN<TA0RUN>
Comparator
TA1REG
)
(Up counter = Q
Shift into register buffer
Q
2
TMP92CM22
TA1OUT
TA1FFCR<TA1FFIE>
TA1FF
Inversion
INTTA0
INTTA1
)
2
Q
2
Q
3
Write TA0REG (Register buffer)
2007-02-16
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