Toshiba TMP92CM22FG TLCS-900/H1 Series Manual page 85

Data Size Start
(Bit) Address
4n + 0
8
4n + 1
4n + 2
4n + 3
4n + 0
16
4n + 1
4n + 2
4n + 3
4n + 0
32
4n + 1
4n + 2
4n + 3
xxxxx During a read, data input to the bus ignored. At write, the bus is at high
:
impedance and the write strobe signal remains inactive.
Data Width in
Memory Side (Bit) Address
8/16
8
16
8/16
8
16
(1) 4n + 0
8
(2) 4n + 1
16
(1) 4n + 1
8
(2) 4n + 2
(1) 4n + 1
16
(2) 4n + 2
(1) 4n + 2
8
(2) 4n + 1
16
(1) 4n + 3
8
(2) 4n + 4
(1) 4n + 3
16
(2) 4n + 4
(1) 4n + 0
8
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 0
16
(2) 4n + 2
(1) 4n + 0
8
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 1
16
(2) 4n + 2
(3) 4n + 4
(1) 4n + 2
8
(2) 4n + 3
(3) 4n + 4
(4) 4n + 5
(1) 4n + 2
16
(2) 4n + 4
(1) 4n + 3
8
(2) 4n + 4
(3) 4n + 5
(4) 4n + 6
(1) 4n + 3
16
(2) 4n + 4
(3) 4n + 6
92CM22-83
CPU Data
CPU
D15 to D8
4n + 0
xxxxx
4n + 1
xxxxx
4n + 1
b7 to b0
4n + 2
xxxxx
4n + 3
xxxxx
4n +3
b7 to b0
xxxxx
xxxxx b15 to b8
4n + 0
b15 to b8
xxxxx
xxxxx b15 to b8
b7 to b0
xxxxx b15 to b8
xxxxx
xxxxx b15 to b8
4n + 2
b15 to b8
xxxxx
xxxxx b15 to b8
b7 to b0
xxxxx b15 to b8
xxxxx
xxxxx b15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b15 to b8
b31 to b24 b23 to b16
xxxxx
xxxxx b15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b7 to b0
b23 to b16 b15 to b8
xxxxx b31 to b24
xxxxx
xxxxx B15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b15 to b8
b31 to b24 b23 to b16
xxxxx
xxxxx b15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b7 to b0
b23 to b16 b15 to b8
xxxxx b31 to b24
TMP92CM22
D7 to D0
b7 to b0
b7 to b0
xxxxx
b7 to b0
b7 to b0
xxxxx
b7 to b0
b7 to b0
b7 to b0
xxxxx
b7 to b0
b7 to b0
b7 to b0
xxxxx
b7 to b0
b7 to b0
b7 to b0
xxxxx
b7 to b0
b7 to b0
b7 to b0
xxxxx
2007-02-16