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BJ72.
Unexpected #UD on VPEXTRD/VPINSRD
Problem:
Execution of the VPEXTRD or VPINSRD instructions outside of 64-bit mode with VEX.W
set to 1 may erroneously cause a #UD (invalid-opcode exception).
Implication:
The affected instructions may produce unexpected invalid-opcode exceptions outside
64-bit mode.
Workaround:
Software should encode VEX.W = 0 for executions of the VPEXTRD and VPINSRD
instructions outside 64-bit mode.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ73.
Restrictions on ECC_Inject_Count Update When Disabling and
Enabling Error Injection
Problem:
The artificial injection of memory ECC errors allows control of the number of injections
through the ECC_Inject_Count (MMIO) register. When using this counter option, if the
transaction count is decreased after the injections were previously enabled the errors
may not be injected properly.
Implication:
Due to this erratum, injected errors may not be logged as expected.
Workaround:
Do not decrease the error counter value if it was previously enabled. Reset should be
applied before decreasing the error count value.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ74.
Successive Fixed Counter Overflows May be Discarded
Problem:
Under specific internal conditions, when using Freeze PerfMon on PMI feature (bit 12 in
IA32_DEBUGCTL.Freeze_PerfMon_on_PMI, MSR 1D9H), if two or more PerfMon Fixed
Counters overflow very closely to each other, the overflow may be mishandled for some
of them. This means that the counter's overflow status bit (in
MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally,
PMI interrupt may be missed if software programs a counter in Sampling-Mode (PMI bit
is set on counter configuration).
Implication:
Successive Fixed Counter overflows may be discarded when Freeze PerfMon on PMI is
used.
Workaround:
Software can avoid this by:
•Avoid using Freeze PerfMon on PMI bit
•Enable only one fixed counter at a time when using Freeze PerfMon on PMI
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ75.
#GP May be Signaled When Invalid VEX Prefix Precedes Conditional
Branch Instructions
Problem:
When a 2-byte opcode of a conditional branch (opcodes 0F8xH, for any value of x)
instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it
may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of a
#UD (illegal opcode) fault.
Implication:
Due to this erratum, #GP fault instead of a #UD may be signaled on an illegal
instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
37
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