Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011 Specification page 28

BJ42. VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When
vex.vvvv !=1111b
Problem: Processor does not signal #UD fault when executing the reserved instruction
VPHMINPOSUW with vex.vvvv !=1111b.
Implication: Executing VPHMINPOSUW with vex.vvvv !=1111b results in the same behavior as
executing with vex.vvvv=1111b.
Workaround: Software should not use VPHMINPOSUW with vex.vvvv !=1111b in order to ensure
future compatibility.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ43. LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST/T-state/S-state/C1E Transition or Adaptive
Thermal Throttling
Problem: The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after a
transition of:
• EIST (Enhanced Intel® SpeedStep Technology)
• T-state (Thermal Monitor states)
• S1-state (ACPI package sleep state)
• C1E (Enhanced C1 Low Power state)
• Adaptive Thermal Throttling
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after a transition of EIST, T-states, S-states, C1E,
or Adaptive Thermal Throttling.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.
BJ44. VMREAD/VMWRITE Instruction May Not Fail When Accessing an
Unsupported Field in VMCS
Problem: The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B states
that execution of VMREAD or VMWRITE should fail if the value of the instruction's
register source operand corresponds to an unsupported field in the VMCS (Virtual
Machine Control Structure). The correct operation is that the logical processor will set
the ZF (Zero Flag), write 0CH into the VM-instruction error field and for VMREAD leave
the instruction's destination operand unmodified. Due to this erratum, the instruction
may instead clear the ZF, leave the VM-instruction error field unmodified and for
VMREAD modify the contents of its destination operand.
Implication: Accessing an unsupported field in VMCS will fail to properly report an error. In addition,
VMREAD from an unsupported VMCS field may unexpectedly change its destination
operand. Intel has not observed this erratum with any commercially available software.
Workaround: Software should avoid accessing unsupported fields in a VMCS
Status: For the steppings affected, see the Summary Tables of Changes.
28 Specification Update