Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011 Specification page 36

BJ68. Processor May Fail to Acknowledge a TLP Request
Problem: When a PCIe root port's receiver is in Receiver L0s power state and the port initiates a
Recovery event, it will issue Training Sets to the link partner. The link partner will
respond by initiating an L0s exit sequence. Prior to transmitting its own Training Sets,
the link partner may transmit a TLP (Transaction Layer Packet). Due to this erratum,
the root port may not acknowledge the TLP request.
Implication: After completing the Recovery event, the PCIe link partner will replay the TLP request.
The link partner may set a Correctable Error status bit, which has no functional effect.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ69. Executing The GETSEC Instruction While Throttling May Result in a
Processor Hang
Problem: If the processor throttles due to either high temperature thermal conditions or due to
an explicit operating system throttling request (TT1) while executing GETSEC[SENTER]
or GETSEC[SEXIT] instructions, then under certain circumstances, the processor may
hang.
Implication: Possible hang during execution of GETSEC instruction. Intel has not been observed this
erratum with any commercially available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ70. PerfMon Event LOAD_HIT_PRE.SW_PREFETCH May Overcount
Problem: PerfMon event LOAD_HIT_PRE.SW_PREFETCH (event 4CH, umask 01H) should count
load instructions hitting an ongoing software cache fill request initiated by a preceding
software prefetch instruction. Due to this erratum, this event may also count when
there is a preceding ongoing cache fill request initiated by a locking instruction.
Implication: PerfMon event LOAD_HIT_PRE.SW_PREFETCH may overcount.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ71. Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a
#NM Exception
Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (Invalid-
Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-not-
available) exception will be raised instead of #UD exception.
Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround: Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status: For the steppings affected, see the Summary Tables of Changes.
36 Specification Update