Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011 Specification page 32

BJ54. A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in
Certain Conditions
Problem: Under specific internal conditions, if software tries to write the IA32_FIXED_CTR1 MSR
(30AH) a value that has all bits [31:1] set while the counter was just about to overflow
when the write is attempted (i.e. its value was 0xFFFF FFFF FFFF), then due to this
erratum the new value in the MSR may be corrupted.
Implication: Due to this erratum, IA32_FIXED_CTR1 MSR may be written with a corrupted value.
Workaround: Software may avoid this erratum by writing zeros to the IA32_FIXED_CTR1 MSR,
before the desired write operation.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ55. Instruction Fetch May Cause Machine Check if Page Size and Memory
Type Was Changed Without Invalidation
Problem: This erratum may cause a machine-check error (IA32_MCi_STATUS.MCACOD=0150H)
on the fetch of an instruction that crosses a 4-KByte address boundary. It applies only
if (1) the 4-KByte linear region on which the instruction begins is originally translated
using a 4-KByte page with the WB memory type; (2) the paging structures are later
modified so that linear region is translated using a large page (2-MByte, 4-MByte, or 1-
GByte) with the UC memory type; and (3) the instruction fetch occurs after the paging-
structure modification but before software invalidates any TLB entries for the linear
region.
Implication: Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (e.g.,
PDE); then invalidate any translations for the affected linear addresses; and then
modify the relevant paging-structure entry to set the P flag and establish the new page
size and memory type.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ56. Reception of Certain Malformed Transactions May Cause PCIe Port to
Hang Rather Than Reporting an Error
Problem: If the processor receives an upstream malformed non posted packet for which the type
field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then
due to this erratum the integrated PCIe controller may hang instead of reporting the
malformed packet error or issuing an unsupported request completion transaction.
Implication: Due to this erratum, the processor may hang without reporting errors when receiving a
malformed PCIe transaction. Intel has not observed this erratum with any commercially
available device.
Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported
requests with 4 DW header formats.
Status: For the steppings affected, see the Summary Tables of Changes.
32 Specification Update