Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - SPECIFICATION UPDATE 01-2011 Specification page 33

BJ57. PCIe LTR Incorrectly Reported as Being Supported
Problem: LTR (Latency Tolerance Reporting) is a new optional feature specified in PCIe rev. 2.1.
The processor reports LTR as supported in LTRS bit in DCAP2 register (bus 0; Device 1;
Function 0; offset 0xc4), but this feature is not supported.
Implication: Due to this erratum, LTR is always reported as supported by the LTRS bit in the DCAP2
register.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ58. PerfMon Overflow Status Can Not be Cleared After Certain Conditions
Have Occurred
Problem: Under very specific timing conditions, if software tries to disable a PerfMon counter
through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event-
select (e.g. MSR 0x186) and the counter reached its overflow state very close to that
time, then due to this erratum the overflow status indication in MSR
IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.
Implication: Due to this erratum, software may be unable to clear the PerfMon counter overflow
status indication.
Workaround: Software may avoid this erratum by clearing the PerfMon counter value prior to
disabling it and then clearing the overflow status indication bit.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ59. XSAVE Executed During Paging-Structure Modification May Cause
Unexpected Processor Behavior
Problem: Execution of XSAVE may result in unexpected behavior if the XSAVE instruction writes
to a page while another logical processor clears the dirty flag or the accessed flag in
any paging-structure entry that maps that page.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ60. C-state Exit Latencies May be Higher Than Expected
Problem: Core C-state exit can be delayed if a P-state transition is requested before the pending
C-state exit request is completed. Under certain internal conditions the core C-state
exit latencies may be over twice the value specified in the Intel® 64 and IA-32
Architectures Optimization Reference Manual.
Implication: While typical exit latencies are not impacted, the worst case core C-state exit latency
may be over twice the value specified in the Intel® 64 and IA-32 Architectures
Optimization Reference Manual and may lead to a delay in servicing interrupts. Intel
has not observed any system failures due to this erratum.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Specification Update 33