ST STM32MP257F-EV1 User Manual page 23

7.8 eMMC flash memory
The 4‑Gbyte eMMC flash memory is compatible with eMMC v5.0.
The eMMC RSTn (NRSTC1MS, active LOW) is the reset for eMMC. The embedded footprint is also compatible
with other eMMC references in the 153‑ball package. Check the compatibility of the memory datasheet with the
MB1936 schematics. The SDMMC2 is a bootable interface.
I/O
PE15
PE14
PE13
PE11
PE8
PE12
PE10
PE9
PE6
PE7
NRSTC1MS
7.9 Mini PCIe
7.9.1 Description
The STM32MP257F-EV1 Evaluation board supports a mini‑PCIE connector. The 100 MHz CLK (REF CLK) can
be generated by the STM32MP2:
• R87, R88, R89, R90, R288, and R328 OFF,
• R77 and R78 ON.
Or by an external 100 MHz clock generator (U33):
• R87, R88, R89, and R90 ON,
• R77, R78, R288, and R328 OFF.
This is the default configuration on the MB1936 board
Or by a device plugged into the mini‑PCIE connector:
• R77, R78, R87, R88, R89, and R90 OFF,
• R288 and R328 ON.
UM3359 - Rev 2
Table 16. eMMCflash memory I/O interface
CMD (eMMC.SDMMC2_CMD)
CLK (eMMC.SDMMC2_CK)
D0(eMMC.SDMMC2_D0)
D1(eMMC.SDMMC2_D1)
D2(eMMC.SDMMC2_D2)
D3(eMMC.SDMMC2_D3)
D4(eMMC.SDMMC2_D4)
D5(eMMC.SDMMC2_D5)
D6(eMMC.SDMMC2_D6)
D7(eMMC.SDMMC2_D7)
Configuration
RSTn
UM3359
Board functions
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