System Cache/Memory; Chipset - NEC DIRECTION SP B - SERVICE MANUAL 1998 Service Manual

1-2 Technical Information

System Cache/Memory

To utilize the processor's power, the system features an optimized 64-bit memory interface
and provides support for a second level cache to compliment the processor's internal cache.
High-performance features include:
T
pipeline 32-bit addressing
T
64-bit data
T
512-KB of pipeline burst secondary cache; direct mapped write-back and
write-through organization.
The system comes with 32 to 384 MB of main system memory. Three sockets on the
system board support up to 384 MB of high-speed memory using industry-standard gold-
plated dual in-line memory modules (DIMMs).
The system supports PC100 Synchronous DRAM (SDRAM) only.
The system supports the following DIMM configurations:
T
1-Mbit by 64 or 1-Mbit by 72 (8-MB DIMM)
T
2-Mbit by 64 or 2-Mbit by 72 (16-MB DIMM)
T
4-Mbit by 64 or 4-Mbit by 72 (32-MB DIMM)
T
8-Mbit by 64 or 8-Mbit by 72 (64-MB DIMM)
T
16-Mbit by 64 or 16-Mbit by 72 (128-MB DIMM).

Chipset

The Intel 440BX chipset provides DMA, memory, and bus control. The chipset includes the
following chips:
T
Intel 82443BX PCI/AGP (PAC)
and data paths for transfers between the processor's host bus, PCI bus,
Accelerated Graphics Port (AGP), and main memory.
T
Intel 82371EB PCI ISA IDE Xccelerator (PIIX4E)
PCI-to-ISA bridge, PCI IDE functionality, Universal Serial Bus (USB) host/hub
functions, and enhanced power management.
provides bus-control signals, address paths,
implements the