ADLINK Technology I-Pi SMARC User Manual page 26

I-Pi-SMARC User's Guide
5.7 PCIe Ports
two PCIe Gen 2.1 ports (PCIE_A and PCIE_B).
Name Pin # Description
PCIE_A_TX+ P89 Differential PCIe link A transmit data pair
PCIE_A_TX- P90
PCIE_A_RX+ P86 Differential PCIe link A receive data pair
PCIE_A_RX- P87
PCIE_A_REFCK+ P83 Differential PCIe Link A reference clock
PCIE_A_REFCK- P84 output
PCIE_A_RST# P75 PCIe Port A reset output
PCIE_A_CKREQ# P78 PCIe Port A clock request
PCIE_B_TX+ S90 Differential PCIe link B transmit data pair
PCIE_B_TX- S91
PCIE_B_RX+ S87 Differential PCIe link B receive data pair
PCIE_B_RX- S88
PCIE_B_REFCK+ S84 Differential PCIe Link B reference clock
PCIE_B_REFCK- S85 output
PCIE_B_RST# S76 PCIe Port B reset output
PCIE_B_CKREQ# P77 PCIe Port B clock request
PCIE_WAKE# S146 PCIe wake up interrupt to host –
common to PCIe links A, B, C, D
Note: The module provides PCIe clock generators for PCIE_A and PCIE_B, thus not external clock source on the carrier is needed.
Page 19
I/O I/O Power
Type Level Domain
O LVDS Runtime
PCIE
I LVDS Runtime
PCIE
O LVDS Runtime
PCIE
O 3.3V Runtime
CMOS
I OD 3.3V Runtime
CMOS
O LVDS Runtime
PCIE
I LVDS Runtime
PCIE
O LVDS Runtime
PCIE
O 3.3V Runtime
CMOS
I OD 3.3V Runtime
CMOS
I OD 3.3V Runtime
CMOS
copyright © 2024 ADLINK Technology Inc.
PU / PD Comments
Series AC coupled on module
Series AC coupled off module
No need for this signal because module
provides onboard PCIe clock
Series AC coupled on module
Series AC coupled off module
No need for this signal because module
provides onboard PCIe clock
PU 10k
SGET SMARC Rev 2.1