ADLINK Technology I-Pi SMARC User Manual page 22

I-Pi-SMARC User's Guide
5.5 Audio
5.5.1 I2S
Pin # Description
Name
I2S0_LRCK S39 I2S0 Left & Right synchronization
clock
I2S0_SDOUT S40 I2S0 Digital audio Output
I2S0_SDIN S41 I2S0 Digital audio Input
I2S0_CK S42 I2S0 Digital audio clock
I2S2_LRCK S50 I2S2 Left & Right synchronization
clock
I2S2_SDOUT S51 I2S2 Digital audio Output
I2S2_SDIN S52 I2S2 Digital audio Input
I2S2_CK S53 I2S2 Digital audio clock
AUDIO_MCK S38 Master clock output to I2S
codec(s)
Note:
1. I2S signals are routed to the Audio Expansion Board pin header.
2. Support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification.
Page 15
I/O I/O Power
Type Level Domain
I/O 1.8V Runtime
CMOS
O 1.8V Runtime
CMOS
I 1.8V Runtime
CMOS
I/O 1.8V Runtime
CMOS
I/O 1.8V Runtime
CMOS
O 1.8V Runtime
CMOS
I 1.8V Runtime
CMOS
I/O 1.8V Runtime
CMOS
O 1.8V Runtime
CMOS
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PU / Comments
PD
Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
Module Output if CPU acts in Master Mode
Module Input if CPU acts in Slave Mode
SGET SMARC Rev 2.1